In general, data receivers implement processing functions to convert a received analog signal to digital values that represent estimates of transmitted data. In state of the art high-rate data receivers, in particular serial line receivers, these processing functions are often realized through a combination of analog signal processing functions, which typically include a line equalization function, followed by a data slicer block that converts the equalized analog signal to binary data. By way of specific example, serial data receivers can implement DFE (decision feedback equalization) functions using either non-integrating DFE summer circuits or sampled current integrator DFE summer circuits, as is well known in the art. However, non-integrating DFE summer circuits are not power efficient for DFE summation functions in high data rate receivers and sampled current integration DFE summer circuits do not provide optimum noise suppression in high data rate receivers.